1. Field of the Invention
The present invention relates to a semiconductor memory having a plurality of banks and to a memory system having this semiconductor memory and a controller.
2. Description of the Related Art
In recent years, the data volume handled by a system apparatus such as a mobile phone has dramatically increased. In accordance therewith, the capacity of a semiconductor memory mounted on the system apparatus has also increased, which has created a demand for a semiconductor memory with a high data transfer rate. A semiconductor memory such as a DRAM having a plurality of banks improves its data transfer rate by operating the banks simultaneously to sequentially read data from the banks. An access cycle of the semiconductor memory for executing a read operation or a write operation once depends on the operation time of a memory core. Therefore, the data transfer rate increases when sequential accesses continue, but it decreases when random accesses frequently occur because data output is interrupted. In order to prevent the data transfer rate from lowering, it is needed to determine, at a development stage of a system, data to be held in the respective banks so that sequential accesses continue. That is, in the prior art, in order to prevent the data transfer rate from lowering, the system side has to be designed so as not to continuously access the same bank.
For example, Japanese Unexamined Patent Application Publication No. Hei 11-283364 describes a technique for comparing a row address currently accessed with an externally supplied new row address and determining that it is in a hit state when these row addresses are the same and that it is in a mistake state when these row addresses are different. This allows a controller accessing a semiconductor memory to use a DRAM as if it is a cache memory.
However, in the technique described in Japanese Unexamined Patent Application Publication No. Hei 11-283364, the data transfer rate lowers since the mistake state frequently occurs when random accesses continue. In order to improve the data transfer rate, it is necessary for the system side to cleverly determine the access order or the like of the semiconductor memory.
As described above, the access cycle of the semiconductor memory depends on the operation time of the memory core. Therefore, even heightening the frequency of clocks cannot improve the data transfer rate at the time of the random access. Thus, there has been no proposal of a method to improve the data transfer rate at the time of the random access without giving any load to the system side.